1. Field of the Invention
The present invention generally relates to a code size reduction method. More specifically, embodiments of the present invention relate to a method to reduce a code size by minimizing the number of times data is moved between a memory and a register.
2. Description of the Related Art
Generally, a central processing unit (CPU) carries out prescribed processes such as operations by use of data stored in a memory. To this end, the CPU utilizes data written in a register that is connected with the CPU, rather than directly using the data in the memory. The data in the memory is written in the register before the CPU utilizes the data in the memory. After carrying out the prescribed processes using the data written in the register, the CPU writes result data acquired from the processes to the register. The result data in the register is stored in the memory according to a given instruction. In short, the CPU has to utilize the register in order to use the data in the memory. The memory and the register respectively are divided into a plurality of regions.
Addresses are assigned to the regions, respectively. FIG. 1 illustrates constructions of the memory and the register. The register is divided into 16 regions, and each region is assigned an address. Addresses r0 through r15 are sequentially assigned to the regions of the register. Likewise, the memory includes divided regions that are assigned addresses, respectively, as in the register. As the size of the memory can vary according to a user's setting, the number of the divided regions also differs. In FIG. 1, one memory is divided into a plurality of regions, and the divided regions are assigned addresses 0x00, 0x04, 0x08, 0x0c, . . . , and so forth.
The following explains how the data stored in the memory is moved to the register. According to an instruction, data stored in a certain region (address) among the data in the memory is transferred to a specific region (address) of the register. Hereinafter, it is described that the term ‘address’ denotes the region to which the given address is assigned. For instance, the data in the address 0x00 of the memory is transferred to and written in the address r0 of the register according to a first instruction. The data in the address 0x04 of the memory is transferred to and written in the address r1 of the register according to a second instruction. A third instruction causes the data in the address 0x08 of the memory to be transferred to and written in the address r2 of the register. To summarize, one unit of data is moved into the register according to one instruction.
The CPU performs prescribed processes using the data written in the register, and rewrites result data corresponding to the processes in the register. The result data in the register are moved to the memory one by one according to a single instruction. To overcome this complexity, a solution is under discussion to transfer more than one unit of data using one instruction, which is referred to as a multiple load/store (MLS).
MLS is described in detail. MLS enables transfer of at least two units of data in the memory to the register using one instruction. However, MLS requires that the addresses of the data read from the memory be arranged in sequence. By way of specific example, given that three data are read from the data stored in the address 0x08, the addresses of the read data are 0x08, 0x0c, and 0x10. Note that the read data are written in contiguous addresses of the register. For example, if the read data are written in addresses starting from r1, the addresses storing the read data become r1, r2, and r3.
In light of the background, the aforementioned requirements should be satisfied to attain MLS. However, it is very rare to read contiguous data from the memory. The data allocated to the addresses of the memory and the register may be rearranged through operations so as to meet the requirement of read data being arranged in sequence, but this solution causes too many operations for the rearrangement.